Such a processor is already known in the art, e.g. from the published European patent application EP 0459412, the scrambling means being referred to as an address generation circuit. In case of a real input data sequence this processor generates superfluous arithmetic results, because the second half of the Fast Fourier Transform output sequence generated is complex conjugated to the first half and may thus be derived therefrom. Thus, for such a real input data sequence, the processor in fact executes a number of unnecessary arithmetic operations and is therefore unnecessary complex. Moreover, the memory means must be quite large in order to store the Fast Fourier Transform output data sequence.